A Data Segment Is to Be Located From Address A000016 to Affff16. What Value Must Be Loaded Into Ds?
MOV--Move
Opcode | Instruction | Description |
|---|---|---|
| 88 / r | MOV r/m8,r8 | Move r8 to r/m8 |
| 89 / r | MOV r/m16,r16 | Motility r16 to r/m16 |
| 89 / r | MOV r/m32,r32 | Move r32 to r/m32 |
| 8A / r | MOV r8,r/m8 | Move r/m8 to r8 |
| 8B / r | MOV r16,r/m16 | Move r/m16 to r16 |
| 8B / r | MOV r32,r/m32 | Move r/m32 to r32 |
| 8C / r | MOV r/m16,Sreg ** | Move segment register to r/m16 |
| 8E / r | MOV Sreg,r/m16 ** | Motion r/m16 to segment annals |
| A0 | MOV AL, moffs8 * | Move byte at ( seg:showtime ) to AL |
| A1 | MOV AX, moffs16 * | Move word at ( seg:offset ) to AX |
| A1 | MOV EAX, moffs32 * | Move doubleword at ( seg:offset ) to EAX |
| A2 | MOV moffs8 *,AL | Move AL to ( seg:start ) |
| A3 | MOV moffs16 *,AX | Move AX to ( seg:commencement ) |
| A3 | MOV moffs32 *,EAX | Movement EAX to ( seg:commencement ) |
| B0+ rb | MOV r8,imm8 | Move imm8 to r8 |
| B8+ rw | MOV r16,imm16 | Motion imm16 to r16 |
| B8+ rd | MOV r32,imm32 | Move imm32 to r32 |
| C6 / 0 | MOV r/m8,imm8 | Movement imm8 to r/m8 |
| C7 / 0 | MOV r/m16,imm16 | Movement imm16 to r/m16 |
| C7 / 0 | MOV r/m32,imm32 | Move imm32 to r/m32 |
Notation
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* The moffs8 , moffs16 , and moffs32 operands specify a unproblematic start relative to the segment base, where 8, 16, and 32 refer to the size of the data. The address-size attribute of the education determines the size of the offset, either 16 or 32 bits.
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** In 32-bit manner, the assembler may insert the 16-chip operand-size prefix with this teaching (run across the post-obit "Clarification" section for further data).
Description
Copies the second operand (source operand) to the first operand (destination operand). The source operand can be an immediate value, full general-purpose register, segment register, or retentiveness location; the destination annals can exist a general-purpose register, segment register, or memory location. Both operands must exist the same size, which tin be a byte, a discussion, or a doubleword.
The MOV instruction cannot be used to load the CS register. Attempting to exercise so results in an invalid opcode exception (#UD). To load the CS register, utilise the far JMP, Telephone call, or RET instruction.
If the destination operand is a segment register (DS, ES, FS, GS, or SS), the source operand must be a valid segment selector. In protected mode, moving a segment selector into a segment register automatically causes the segment descriptor information associated with that segment selector to be loaded into the subconscious (shadow) part of the segment register. While loading this data, the segment selector and segment descriptor data is validated (see the "Operation" algorithm below). The segment descriptor data is obtained from the GDT or LDT entry for the specified segment selector.
A null segment selector (values 0000-0003) tin be loaded into the DS, ES, FS, and GS registers without causing a protection exception. Nonetheless, any subsequent attempt to reference a segment whose corresponding segment register is loaded with a null value causes a general protection exception (#GP) and no memory reference occurs.
Loading the SS register with a MOV instruction inhibits all interrupts until later the execution of the next instruction. This operation allows a stack arrow to be loaded into the ESP annals with the next didactics (MOV ESP, stack-arrow value ) before an interrupt occurs. The LSS instruction offers a more than efficient method of loading the SS and ESP registers.
When operating in 32-bit mode and moving information between a segment register and a full general-purpose annals, the Intel(R) Compages 32-bit processors practise non crave the use of the 16-bit operand-size prefix (a byte with the value 66H) with this instruction, just virtually assemblers volition insert it if the standard class of the pedagogy is used (for example, MOV DS, AX). The processor will execute this educational activity correctly, but it will unremarkably crave an extra clock. With most assemblers, using the instruction form MOV DS, EAX will avert this unneeded 66H prefix. When the processor executes the education with a 32-fleck general-purpose annals, it assumes that the xvi least-meaning bits of the general-purpose register are the destination or source operand. If the register is a destination operand, the resulting value in the 2 loftier-order bytes of the register is implementation dependent. For the Pentium(R) Pro processor, the ii high-lodge bytes are filled with zeros; for earlier 32-flake Intel
Operation
DEST SRC;
Loading a segment register while in protected mode results in special checks and actions, every bit described in the following listing. These checks are performed on the segment selector and the segment descriptor it points to.
IF SS is loaded;
THEN
IF segment selector is null
THEN #GP(0);
FI;
IF segment selector index is outside descriptor table limits
OR segment selector's RPL CPL
OR segment is non a writable data segment
OR DPL CPL
THEN #GP(selector);
FI;
IF segment not marked nowadays
Then #SS(selector);
ELSE
SS segment selector;
SS segment descriptor;
FI;
FI;
IF DS, ES, FS, or GS is loaded with non-null selector;
THEN
IF segment selector index is outside descriptor table limits
OR segment is not a data or readable lawmaking segment
OR ((segment is a information or nonconforming code segment)
AND (both RPL and CPL > DPL))
So #GP(selector);
IF segment not marked present
And then #NP(selector);
ELSE
SegmentRegister segment selector;
SegmentRegister segment descriptor;
FI;
FI;
IF DS, ES, FS, or GS is loaded with a null selector;
And then
SegmentRegister segment selector;
SegmentRegister segment descriptor;
FI;
Flags Affected
None.
Protected Mode Exceptions
#GP(0) - If attempt is made to load SS register with zero segment selector. If the destination operand is in a nonwritable segment. If a retentiveness operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS annals contains a null segment selector.
#GP(selector) - If segment selector index is outside descriptor table limits. If the SS register is being loaded and the segment selector's RPL and the segment descriptor'due south DPL are not equal to the CPL. If the SS register is being loaded and the segment pointed to is a nonwritable data segment. If the DS, ES, FS, or GS register is existence loaded and the segment pointed to is non a data or readable lawmaking segment. If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or nonconforming lawmaking segment, only both the RPL and the CPL are greater than the DPL.
#SS(0) - If a memory operand effective address is outside the SS segment limit.
#SS(selector) - If the SS annals is existence loaded and the segment pointed to is marked non present.
#NP - If the DS, ES, FS, or GS register is being loaded and the segment pointed to is marked non present.
#PF(mistake-code) - If a page fault occurs.
#AC(0) - If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is three.
#UD - If attempt is fabricated to load the CS register.
Real-Address Mode Exceptions
#GP - If a memory operand effective address is exterior the CS, DS, ES, FS, or GS segment limit.
#SS - If a memory operand effective address is outside the SS segment limit.
#UD - If attempt is made to load the CS register.
Virtual-8086 Mode Exceptions
#GP(0) - If a retention operand effective address is exterior the CS, DS, ES, FS, or GS segment limit.
#SS(0) - If a memory operand effective accost is outside the SS segment limit.
#PF(error-code) - If a page error occurs.
#Air-conditioning(0) - If alignment checking is enabled and an unaligned memory reference is made.
#UD - If attempt is made to load the CS register.
For details, see Book 2A and Volume 2B of the Intel(R) 64 and IA-32 Intel Compages Software Developer's Manual . For the latest updates on the instruction gear up data, become to the web site.
Source: http://www.nacad.ufrj.br/online/intel/vtune/users_guide/mergedProjects/analyzer_ec/mergedProjects/reference_olh/mergedProjects/instructions/instruct32_hh/vc177.htm